參數(shù)資料
型號(hào)： MQ80C52CXXX-25/883:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
封裝： CERAMIC, QFP-44
文件頁數(shù)： 73/170頁
文件大?。?/td> 25028K
164
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
17.11.9
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization mode
Writing the TSM bit to one, activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keepeing the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-
chronization Mode” on this page for a description of the Timer/Counter Synchronization mode.
Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except ifthe TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Bit
7
6
5
4
3
2
1
0
TSM
–
PSRASY
PSRSYNC
GTCCR
Read/Write
R/W
R
R/W
Initial Value
0
相關(guān)PDF資料
PDF描述
MQ80C52TXXX-16:RD 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
MR80C52CXXX-25/883:RD 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
MR80C52TXXX-25SHXXX:R 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
MC80C32-16SHXXX:D 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40
MD80C52EXXX-25/883:D 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
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