參數(shù)資料
型號(hào)： MQ80C52EXXX-25:R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
封裝： CERAMIC, QFP-44
文件頁(yè)數(shù)： 62/83頁(yè)
文件大?。?/td> 8336K
75
7707F–AVR–11/10
AT90USB82/162
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is
used as data output line for the AT90USB82/162.
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB3 bit.
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source.
PDI/MOSI/PCINT2 – Port B, Bit 2
PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used
as data input line for the AT90USB82/162.
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB2 bit.
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source.
SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit. This pin also serves as
Clock for the Serial Programming interface.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.
SS/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 11-4 and Table 11-5 relate the alternate functions of Port B to the overriding signals
shown in Figure 11-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source
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