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參數(shù)資料
| 型號： | MQ80C52EXXX-25:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 7/83頁 |
| 文件大?。?/td> | 8336K |
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15
8021G–AVR–03/11
ATmega329P/3290P
6.6.1
SPH and SPL – Stack pointer High and Stack Pointer Low
6.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The
Atmel
AVR CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock
source for the chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
1514131211
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
76
543210
Read/Write
R/W
R/WR/W
R/W
Initial Value
0
000000
00
000000
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
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