參數(shù)資料
型號(hào): MQ80C52TXXX-12SB
廠商: TEMIC SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù): 16/46頁(yè)
文件大?。?/td> 4720K
代理商: MQ80C52TXXX-12SB
22
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1.
Write the signature for change enable of protected I/O register to register CCP
2.
Within four instruction cycles, write the desired value to CLKPS bits
At start-up, the CLKPS bits will be reset to 0b0011 to select the clock division factor of 8. The application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum
frequency of the device at the present operating conditions.
6.5.3
OSCCAL – Oscillator Calibration Register
.
Bits 7:0
CAL[7:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the
oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to
the range given is not guaranteed.
The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a
setting of 0xFF gives the highest frequency.
1
0
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
Bit
765432
1
0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
Initial Value
0
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