參數(shù)資料
型號(hào)： MQ80C52TXXX-12SB
廠商： TEMIC SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)： 6/46頁(yè)
文件大小： 4720K
代理商： MQ80C52TXXX-12SB
13
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
4.8
Register Description
4.8.1
CCP – Configuration Change Protection Register
Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles.
All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU,
and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP0 will read as one as long as the protected feature is enabled,
while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are recognised.
Table 4-1.
Signatures Recognised by the Configuration Change Protection Register
Notes: 1. Only WDE and WDP[3:0] bits are protected in WDTCSR.
2. Only BODS bit is protected in MCUCR.
4.8.2
SPH and SPL — Stack Pointer Registers
Bits 7:0 – SP[7:0]: Stack Pointer
The Stack Pointer register points to the top of the stack, which is implemented growing from higher memory locations to
lower memory locations. Hence, a stack PUSH command decreases the stack pointer.
The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled.
In ATtiny20, the SPH register has not been implemented.
Bit
76543210
CCP[7:0]
CCP
Read/Write
WWWWWWW
R/W
Initial Value
00000000
Signature
Group
Description
0xD8
IOREG: CLKMSR, CLKPSR, WDTCSR(1), MCUCR(2)
Protected I/O register
Initial Value
00000000
Read/Write
R
RRRRR
Bit
15
14
13
12
11
10
9
8
––––––––
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
Bit
76543210
Read/Write
R/W
Initial Value
RAMEND
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