200
7734Q–AVR–02/12
AT90PWM81/161
16.4.4
ACnECON - Analog Comparator n Extended Control Register
Bit 7..6– Reserved
Bit 5– AC1OI: Analog Comparator n Output Invert
Set this bit to invert the analog comparator n output.
Clear this bit to keep the analog comparator n output.
Bit 4– AC1OE: Analog Comparator n Output Enable
Set this bit to enable the analog comparator n output pin.
Clear this bit to disable the analog comparator n output pin.
Bit 3 – AC1ICE: Analog Comparator 1 Interrupt Capture Enable bit
Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator event.
The comparator output is in this case directly connected to the input capture front-end logic,
making the comparator utilize the noise canceler and edge select features of the
Timer/Counter1 Input Capture interrupt. To make the comparator trigger the Timer/Counter1
Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.
rising edge of AC3O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to
zero, it is the falling edge which is taken into account.
Clear this bit to disable this function. In this case, no connection between the Analog Compara-
tor and the input capture function exists.
Bit 2, 1, 0– ACnH2, ACnH1, ACnH0: Analog Comparator n Hysteresis select
These 3 bits determine the hysteresis value of the analog comparator.
Bit
7
6
543
2
1
0
ACnOI
ACnOE
AC1ICE
ACnH2
ACnH1
ACnH0
ACnECON
Read/Write
R/W
Initial Value
0
Table 16-7.
Analog cComparator n hysteresis selection.
AC1M2
AC1M1
AC1M0
Description
000No hysteresis
001Hysteresis + 10mV
010Hysteresis - 10mV
011Hysteresis ±10mV
100Reserved
101Hysteresis + 25mV
110Hysteresis - 25mV
111Hysteresis ±25mV