
173
7734Q–AVR–02/12
AT90PWM81/161
13.23.6
PCNF0 - PSCR Configuration Register
Bit 7 - PFIFTY0: PSCR Fifty
Writing this bit to one, set the PSCR in a fifty percent mode where only OCR0RBH/L and
OCR0SBH/L are used. They are duplicated in OCR0RAH/L and OCR0SAH/L during the update
of OCR0RBH/L. This feature is useful to perform fifty percent waveforms.
Bit 6 - PALOCK0: PSCR Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and
the PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The
update of the PSCR internal registers will be done at the end of the PSCR cycle if the Output
Compare Register RB has been the last written.
When set, this bit prevails over LOCK (bit 5).
Bit 5 – PLOCK0: PSCR Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2
and the PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles.
The update of the PSCR internal registers will be done if the LOCK bit is released to zero.
Bit 4:3 – PMODE01: 0: PSCR Mode
Select the mode of PSC.
Bit 2 – POP0: PSCR Output Polarity
If this bit is cleared, the PSCR outputs are active Low.
If this bit is set, the PSCR outputs are active High.
Bit 1 – PCLKSEL0: PSCR Input Clock Select
This bit is used to select between CLKPF or CLKPS clocks.
Set this bit to select the fast clock input (CLKPF).
Clear this bit to select the slow clock input (CLKPS).
Bit 0 – Reserved
Bit
7
6
5
4
3210
PFIFTY0
PALOCK0
PLOCK0
PMODE01 PMODE00 POP0
PCLKSEL0 -
PCNF0
Read/Write
R/W
Initial Value
0
0000
Table 13-11. PSCR mode selection.
PMODE01
PMODE00
Description
0
One Ramp mode
01Two Ramp mode
1
0
Four Ramp mode
11Reserved