97
7734Q–AVR–02/12
AT90PWM81/161
11.8
16-bit Timer/Counter Register Description
11.8.1
TCCR1B - Timer/Counter1 Control Register B
Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
Bit 5 – Reserved
Bit 3 – Reserved
Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Bit
7
6
5
4
3
210
ICNC1
ICES1
-
WGM13
-
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
Bit 4 – WGM13: Waveform Generation Mode
Table 11-1.
Waveform generation mode bit description.
Mode
WGM13
Timer/counter mode of
operation
TOP
TOV1 flag
set on
0
Normal
0xFFFF
MAX
12
1
CTC
ICR1
MAX
Table 11-2.
Clock select bit description.
CS12
CS11
CS10
Description
0
No clock source (Timer/Counter stopped)
001
clkI/O/1 (No prescaling)
010
Reserved