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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
10.11 Register description
10.11.1
SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in
Table 10-2.
Note:
1. Standby mode is only recommended for use with external XTALs or resonators.
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is exe-
cuted. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
10.11.2
MCUCR – MCU Control Register
Note:
1. Only available in the Atmel ATmega165PA/325PA/3250PA/645P/6450P picoPower devices.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
Table 10-1 on page 37. Writ-
ing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD in
relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be
set to one and BODSE must be set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active
in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock
cycles.
Bit
765
432
10
0x33 (0x53)
–
SM2
SM1
SM0
SE
SMCR
Read/Write
RR
R/W
Initial Value
000
00
Table 10-2.
Sleep mode select.
SM2
SM1
SM0
Sleep mode
00
0
Idle
0
1
ADC Noise Reduction
0
1
0
Power-down
01
1
Power-save
1
0
Reserved
1
0
1
Reserved
1
0
1
Reserved
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
JTD
BODSE
PUD
–
IVSEL
IVCE
MCUCR
Read/Write
R/W
RR
R/W
Initial Value
0