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型號(hào)：	MQ83C154TXXX-16P883
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	50/839頁(yè)
文件大小：	61013K
代理商：	MQ83C154TXXX-16P883

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always

shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In –

Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave

Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by

user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the

SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gen-

erator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is

driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not

be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been com-

pletely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR

reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 19-2. SPI Master-slave interconnection.

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that

bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When

receiving data, however, a received character must be read from the SPI Data Register before the next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of

the clock signal, the minimum low and high periods should be:

Low period: longer than 2 CPU clock cycles.

High period: longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to

1. See ”Alternate functions of Port B” on page 68 for a detailed description of how to define the direction of the user

defined SPI pins.

Table 19-1.

SPI Pin Overrides

Direction, Master SPI

Direction, Slave SPI

User Defined

User Defined

User Defined

User Defined

相關(guān)PDF資料	PDF描述
MQ83C154TXXX-L16P883	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
MQ83C154XXX-L16P883D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
MR83C154CXXX-20/883	8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44
MQ83C154CXXX-25P883	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
MR83C154TXXX-30/883D	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44

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