139
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Table 18-4 shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored,
Table 18-5 shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to phase correct PWM mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored,
Bit 2:0 – CS2[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Table 18-6.
18.11.2
TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock. Modify-
Table 18-4.
Compare Output Mode, Fast PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
Reserved
1
0
Clear OC2A on compare match, set OC2A at BOTTOM (non-inverting mode).
1
Set OC2A on compare match, clear OC2A at BOTTOM (inverting mode).
Table 18-5.
Compare Output Mode, Phase Correct PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
Reserved
10
Clear OC2A on compare match when up-counting. Set OC2A on compare match when down
counting.
11
Set OC2A on compare match when up-counting. Clear OC2A on compare match when down
counting.
Table 18-6.
Clock Select Bit description.
CS22
CS21
CS20
Description
0
No clock source (Timer/Counter stopped)
00
1
clkT2S/(No prescaling)
01
0
clkT2S/8 (From prescaler)
01
1
clkT2S/32 (From prescaler)
10
0
clkT2S/64 (From prescaler)
10
1
clkT2S/128 (From prescaler)
11
0
clkT2S/256 (From prescaler)
11
1
clk
T
2S/1024 (From prescaler)
Bit
7654
321
0
(0xB2)
TCNT2[7:0]
TCNT2
Read/Write
R/W
Initial Value
0000
000
0