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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
10. Power management and sleep modes
10.1
Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
10.2
Sleep modes
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P, and their distribution. The figure is
helpful in selecting an appropriate sleep mode.
Table 10-1 shows the different sleep modes and their wake up
sources and BOD disable ability
Note:
1. BOD disable is only available for ATmega165PA/325PA/3250PA/645P/6450P.
Notes:
1. Only recommended with external XTAL or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode will be activated by the
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruc-
tion following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
10.3
the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to dis-
consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in soft-
ware, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep
period.
Table 10-1.
Active clock domains and wake-up sources in the different sleep modes.
Active clock domains
Oscillators
Wake-up sources
Software
BOD
d
isab
le
Sleep mode
clk
CP
U
clk
FLA
SH
clk
IO
clk
AD
C
clk
AS
Y
Main
Cloc
k
Sou
rce
en
ab
led
Ti
mer
osc
.
en
ab
led
IN
T0
a
n
d
pi
n
c
h
an
g
e
USI
star
t
co
ndit
ion
Ti
mer2
SPM/
EEPR
OM
Read
y
ADC
Ot
her
I/O
Idle
XXX
X
X
XXX
X
ADC NRM
X
XX
Power-down
XX
Power-save
X
XX
X
XX