95
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
15.9.2
TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modify-
ing the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between
TCNT0 and the OCR0A Register.
15.9.3
OCR0A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0A pin.
15.9.4
TIMSK0 – Timer/Counter 0 Interrupt Mask Register
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Com-
pare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0
occurs, that is, when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
Table 15-6.
Clock Select Bit description.
CS02
CS01
CS00
Description
0
No clock source (Timer/Counter stopped)
001
clkI/O/(No prescaling)
010
clkI/O/8 (From prescaler)
011
clkI/O/64 (From prescaler)
100
clkI/O/256 (From prescaler)
101
clkI/O/1024 (From prescaler)
1
0
External clock source on T0 pin. Clock on falling edge.
1
External clock source on T0 pin. Clock on rising edge.
Bit
765
432
10
0x26 (0x46)
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
000
00
Bit
765
432
10
0x27 (0x47)
OCR0A[7:0]
OCR0A
Read/Write
R/W
Initial Value
000
00
Bit
7654
32
1
0
(0x6E)
–
–OCIE0A
TOIE0
TIMSK0
Read/Write
RRR
R/W
Initial Value
0000
00
0