參數(shù)資料
型號(hào): MR80C32E-36:D
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁(yè)數(shù): 136/336頁(yè)
文件大?。?/td> 8801K
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220
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX
can be safely updated in the following ways:
1.
When ADATE or ADEN is cleared.
2.
During conversion, with taking care of the trigger source event, when it is possible.
3.
After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
21.5.1
ADC input channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The channel selection
may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the
conversion to complete before changing the channel selection
In Free Running mode, always select the channel before starting the first conversion. The channel selection
may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the
first conversion to complete, and then change the channel selection. Since the next conversion has already
started automatically, the next result will reflect the previous channel selection. Subsequent conversions will
reflect the new channel selection
In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not
possible to use the free running mode, unless ADSC bit is set again by soft at the end of each conversion
21.5.2
ADC voltage reference
The reference voltage for the ADC (V
REF) indicates the conversion range for the ADC. Single ended channels that
exceed V
REF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or
external AREF pin.
AV
CC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the inter-
nal bandgap reference (V
BG) through an internal amplifier. In either case, the external AREF pin is directly
connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor
between the AREF pin and ground. V
REF can also be measured at the AREF pin with a high impedance voltmeter.
Note that V
REF is a high impedance source, and only a capacitive load should be connected to the system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage
options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the
AREF pin, the user may switch between AV
CC and 2.56V as reference selection. The first ADC conversion result
after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
AREF pin is alternate function with ISRC Current Source output. When current source is selected, the AREF pin is
not connected to the internal reference voltage network. See AREFEN and ISRCEN bits in Section “ADCSRB –
If differential channels are used, the selected reference should not be closer to AV
CC than indicated in Table 28-8
21.6
ADC noise canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the
CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To
make use of this feature, the following procedure should be used:
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