195
32000D–04/2011
AVR32
LDDPC – Load PC-relative with Displacement
Architecture revision:
Architecture revision1 and higher.
Description
Performs a PC relative load of a register
Operation:
I.
Rd
← *( (PC && 0xFFFF_FFFC) + (ZE(disp7) << 2));
Syntax:
I.
lddpc
Rd, PC[disp]
Operands:
I.
d
∈ {0, 1, …, 15}
disp
∈ {0, 4, …, 508}
Status Flags:
Q:
Not affected.
V:
Not affected.
N:
Not affected.
Z:
Not affected.
C:
Not affected.
Opcode:
01001
disp7
Rd
15
13
12
11
10
4
3
0