- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25637 > MR80C52TXXX-30SBD (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 PDF資料下載
參數(shù)資料
| 型號： | MR80C52TXXX-30SBD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 138/141頁 |
| 文件大?。?/td> | 7628K |
| 代理商： | MR80C52TXXX-30SBD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁當前第138頁第139頁第140頁第141頁
66
2486AA–AVR–02/2013
ATmega8(L)
External
Interrupts
The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the
interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides a
way of generating a software interrupt. The external interrupts can be triggered by a falling or ris-
ing edge or a low level. This is set up as indicated in the specification for the MCU Control
Register – MCUCR. When the external interrupt is enabled and is configured as level triggered,
the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT0 and INT1 requires the presence of an I/O clock, described in “Clock
Systems and their Distribution” on page 25. Low level interrupts on INT0/INT1 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 s (nominal) at 5.0V and 25
C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in “Electrical Characteristics – TA = -40°C to 85°C” on page
235. The MCU will wake up if the input has the required level during this sampling or if it is held
until the end of the start-up time. The start-up time is defined by the SUT Fuses as described in
“System Clock and Clock Options” on page 25. If the level is sampled twice by the Watchdog
Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but
no interrupt will be generated. The required level must be held long enough for the MCU to com-
plete the wake up to trigger the level interrupt.
MCU Control Register
– MCUCR
The MCU Control Register contains control bits for interrupt sense control and general MCU
functions.
Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corre-
sponding interrupt mask in the GICR are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in Table 31. The value on the INT1 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Bit
765
4321
0
SE
SM2
SM1
SM0
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
000
0000
0
Table 31. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
The low level of INT1 generates an interrupt request
0
1
Any logical change on INT1 generates an interrupt request
1
0
The falling edge of INT1 generates an interrupt request
1
The rising edge of INT1 generates an interrupt request
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C52EXXX-12/883:R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52XXX-12 | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MF180C51T-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| MR80C32-12:D | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C32E-36:D | 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。