參數(shù)資料
型號: MR80C52TXXX-30SBD
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 64/141頁
文件大?。?/td> 7628K
代理商: MR80C52TXXX-30SBD
242
32117D–AVR-01/12
AT32UC3C
14.7.11
Trigger Interrupt Mask Register
Name:
TRIMR0 - TRIMR1
Access Type:
Read-only
Offset:
0x080 - 0x084
Reset Value:
0x00000000
TRIM: Trigger Interrupt Mask
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in TRIDR is written to one.
This bit is set when the corresponding bit in TRIER is written to one.
Note:
Channels 0 to 31 are controlled by TRIMR0.
Channels 32 to 63 are controlled by TRIMR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31
30
29
28
27
26
25
24
TRIM
23
22
21
20
19
18
17
16
TRIM
15
14
13
12
11
10
9
8
TRIM
76
543
21
0
TRIM
相關PDF資料
PDF描述
MR80C52EXXX-12/883:R 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
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