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參數(shù)資料
| 型號(hào)： | MS52C182A |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 65,536-Word × 16-Bit or 131,072-Word × 8-Bit STATIC RAM +524,288-Word × 16-Bit or 1,048,576-Word × 8-Bit One Time PROM(64k字×16位或128k字×8位靜態(tài)RAM+512k字×16位或1M字×8位 OTPROM) |
| 中文描述： | 65,536字× 16位或131,072詞× 8位靜態(tài)RAM 524,288詞× 16位或1048576，字× 8位一次性可編程（64k的字× 16位或128K的字× 8位靜態(tài)內(nèi)存為512k字× 16位或100萬字× 8位OTPROM） |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 140K |
| 代理商： | MS52C182A |
2. OE may be either of "H" or "L" in the write cycle of SRAM.
3.
t
AS is specified from CEs="L" or WE="L" , whichever occurs last.
4.
t
WP is an overlap time of CEs="L" and WE="L".
5.
t
WR ,
t
DS ,
t
DH are specified from CEs="H" or WE="H" , whichever occurs first.
6.
t
WHZ is specified by the time when DATA output is floating , not defined by the output level.
7. When I/O pins are in the output mode , don't apply the inverted input signal to the output pins.
MS52C182A
SRAM Data Retention Characteristics
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
(Ta=-20 to 70
°
C)
V
CC
2.7V
V
IH
V
CCH
CEs
0V
CEs
≥
V
CC-
0.2V
t
CDR
t
R
Data Retention Mode
CEo
≥
V
CC-
0.2V
CEs
≥
V
CC-
0.2V
V
IN
=0 to V
CC
V
CC
=1.5V
CEo
≥
V
CC-
0.2V
CEs
≥
V
CC-
0.2V
V
IN
=0 to V
CC
1.5
3
V
μ
A
nS
mS
0
5
V
CCH
I
CCH
t
CDR
t
R
Data Retention Power
Supply Voltage
Data Retention Power
Supply Current
Operation
Recovery Time
Chip Deselect to Data
Retention Time
Notes : 1. A write cycle of SRAM occurs during the overlap of CEo="H" , CEs="L" and WE="L".
12
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