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參數(shù)資料
| 型號： | MS81V06160 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | DRAM |
| 英文描述： | (401,408-word ⅴ 16-bit) FIFO memory |
| 中文描述： | （401408字ⅴ16位），F(xiàn)IFO存儲器 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | MS81V06160 |
Semiconductor
MS81V06160
(401,408-word
×
16-bit) FIFO memory
This version: Sep. 2000
Preliminary
1/18
GENERAL DESCRIPTION
The MS81V06160 is a 6Mb FIFO (First-In First-Out) memory designed for 401,408-words
×
16-bit high-speed
asynchronous read/write operation.
The MS81V06160 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large
memory , and is not designed for high end use in professional graphics systems, which require long term picture
storage and data storage.
The MS81V06160 is provided with independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported, which allow alternate data rates between write and read data streams.
The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write
operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is
possible every cycle time.
Additionally, a write mask function by IE pin and a read-data skipping function by OE pin implement image data
processing easily.
The MS81V06160 provides high speed FIFO (First-in First-out) operation without external refreshing:
MS81V06160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
The MS81V06160’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by
reset timing. The delay length and the number of read delay clocks between write and read, is determined by
externally controlled write and read reset timings. The MS81V06160 uses a thin and small 70-pin plastic TSOP.
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