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參數(shù)資料
| 型號(hào)： | MS7202AL |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Dual-port Static RAM Based CMOS First-In/First-Out (FIFO) Memories Organized(基于雙端口靜態(tài)RAM的CMOS先進(jìn)先出存儲(chǔ)器) |
| 中文描述： | 雙端口靜態(tài)存儲(chǔ)器的CMOS先進(jìn)先出（FIFO）的記憶有組織（基于雙端口靜態(tài)RAM的的的CMOS先進(jìn)先出存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大小： | 80K |
| 代理商： | MS7202AL |
10
MS7200L/7201AL/7202AL
MOSEL V ITELIC
Width Expansion Mode
Word width may be expanded by connecting the
corresponding control input signals of multiple
devices together. The EMPTY, HALF FULL and
FULL FLAGS (
EE
,
HF
and
FF
) can be detected by
MS7200L/01AL/02AL Rev. 1.0 January 1995
any particular device. Figure 4 shows an 18 bit wide
configuration using two devices. They may be
configured to any word width in this manner.
Figure 4. Width Expansion Mode
NOTES:
Flag detection is accomplished by monitoring the
EF
,
HF
and
EF
pins on the device used in
the Width Expansion Mode. Do not connect output control signals together.
DATA IN
WRITE
READ
FULL FLAG
RESET
(W)
(D)
(FF)
(RS)
(R)
(Q)
(EF)
(RT)
7MS
0-8
7MS
9-17
DATA OUT
XI
9
9
9
9
18
18
EMPTY FLAG
XI
RETRANSMIT
(HF) HALF FULL FLAG
HALF FULL FLAG (HF)
Depth Expansion (Daisy Chain) Mode
Word depths may be expanded in multiples of
512 words by Daisy Chaining the devices together
as follows:
1. The FIRST LOAD (
FL
) control signal of the first
device must be grounded. This FIFO repre-
sents word 1-512.
2. All other devices in the Daisy Chain must have
the FIRST LOAD (
FL
) control signal tied to V
CC
in the inactive-high state.
3. The EXPANSION OUT (
XO
) pin of each device
must be connected to the EXPANSION IN (
XI
)
pin of the next device as shown in Figure 5.
4. External logic is required to generate a com-
mon FULL FLAG (
FF
) and EMPTY FLAG (
EF
)
signal by ORing all of the
FF
s together and
ORing all of the
EF
s together.
5. The RETRANSMIT (
RT
) fuction and HALF
FULL FLAG (
HF
) are not available in Daisy
Chain Mode.
W
MS
1025-
1536
FF
EF
XO
MS
1513-
1024
FF
EF
XO
MS
1-512
FF
EF
XO
XI
XI
XI
FL
FL
FL
RS
FULL
D
Q
EMPTY
VCC
R
9
9
9
9
9
Figure 5. Diagram of a 1536 x 9 FIFO in Depth Expansion Mode
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