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參數(shù)資料
| 型號： | MS7202AL |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Dual-port Static RAM Based CMOS First-In/First-Out (FIFO) Memories Organized(基于雙端口靜態(tài)RAM的CMOS先進先出存儲器) |
| 中文描述： | 雙端口靜態(tài)存儲器的CMOS先進先出（FIFO）的記憶有組織（基于雙端口靜態(tài)RAM的的的CMOS先進先出存儲器） |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 80K |
| 代理商： | MS7202AL |
5
MS7200L/7201AL/7202AL
Key to Switching Waveforms
MOSEL V ITELIC
AC Test Conditions
MS7200L/01AL/02AL Rev. 1.0 January 1995
INCLUDING
JIG AND
SCOPE
Figure 1a
30pF
R2
255
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5pF
R2
255
R1 480
5V
OUTPUT
Figure 1b
167
OUTPUT
THEVENIN EQUIVALENT
Equivalent to:
ALL INPUT PULSES
90%
90%
10%
10%
5 ns
5 ns
GND
3.0V
1.73V
Figure 2
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE
AC Test Loads and Waveforms
Timing Waveforms
Input Pulse Levels
0V~ 3.0V
Input Rise and Fall Times
5 ns
Timing Reference Level
1.5V
RS
t
RS
t
RSS
t
RSC
t
EFL
t
RSR
t
HFH
, t
FFH
t
RSS
W
EF
HF, FF
R
RESET
Q0-Q8
t
RC
t
A
t
RPW
t
RR
t
RLZ
t
DV
t
RHZ
t
A
READ
DATA VALID
READ
DATA VALID
R
ASYNCHRONOUS READ OPERATION
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