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| 型號： | MSC7115VM1000 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC1400 內(nèi)核 |
| 接口： | 主機(jī)接口，I²C，UART |
| 時(shí)鐘速率： | 266MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 400kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 400-MAPBGA（17x17） |
| 包裝： | 托盤 |
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MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Specifications
Freescale Semiconductor
22
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 14 summarizes this
restriction.
2.5.3
Reset Timing
The MSC7115 device has several inputs to the reset logic. All MSC7115 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 15 describes the reset sources.
Table 16 summarizes the reset actions that occur as a result of the different reset sources.
Table 13. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Resulting
Division
Factor
Allowed Range
of Core Clock
Comments
11
1
Reserved
11
0
2
150
≤ Core_Clk ≤ 200 MHz
Limited by range of PLL
01
1
2
150
≤ Core_Clk ≤ 200 MHz
Limited by range of PLL
01
0
4
75
≤ Core_Clk ≤ 150 MHz
Limited by range of PLL
Note:
This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL].
Table 14. Core Clock Ranges When Using DDR
DDR Type
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
Comments
DDR 200 (PC-1600)
83–100 MHz
166
≤ core clock ≤ 200 MHz
Core limited to 2
× maximum DDR frequency
DDR 266 (PC-2100)
83–133 MHz
166
≤ core clock ≤ 266 MHz
Core limited to 2
× maximum DDR frequency
DDR 333 (PC-2600)
83–150 MHz
166
≤ core clock ≤ 300 MHz
Core limited to 2
× maximum DDR frequency
Table 15. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC7115 and configures various attributes of the
MSC7115. On PORESET, the entire MSC7115 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC7115. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset
Internal
When the MSC7115 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
Internal
When the MSC7115 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
HIGHZ command
Internal
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
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