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| 型號： | MSC7115VM1000 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC1400 內(nèi)核 |
| 接口： | 主機接口，I²C，UART |
| 時鐘速率： | 266MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 400kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA |
| 供應商設備封裝： | 400-MAPBGA（17x17） |
| 包裝： | 托盤 |
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Specifications
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
25
2.5.4.2
DDR DRAM Output AC Timing Specifications
Table 19 and Table 20 list the output AC timing specifications and measurement conditions for the DDR DRAM interface.
Table 19. DDR DRAM Output AC Timing
No.
Parameter
Symbol
Min
Max
Unit
Mask Set
1L44X
Mask Set
1M88B
200
CK cycle time, (CK/CK crossing)1
100 MHz (DDR200)
133 MHz (DDR266)
tCK
10
Not applicable
1.0
7.52
—
ns
204
An/RAS/CAS/WE/CKE output setup with respect to
CK
tDDKHAS
0.5
× tCK – 2250
0.5
× tCK – 1000
—
ps
205
An/RAS/CAS/WE/CKE output hold with respect to CK
tDDKHAX
0.5
× tCK – 1250
0.5
× tCK – 1000
—
ps
206
CSn output setup with respect to CK
tDDKHCS
0.5
× tCK – 2250
0.5
× tCK – 1000
—
ps
207
CSn output hold with respect to CK
tDDKHCX
0.5
× tCK – 1250
0.5
× tCK – 1000
—
ps
208
CK to DQSn2
tDDKHMH
–600
600
ps
209
Dn/DQMn output setup with respect to DQSn3
tDDKHDS,
tDDKLDS
0.25
× tMCK –
1050
0.25
× tCK – 750
—
ps
210
Dn/DQMn output hold with respect to DQSn3
tDDKHDX,
tDDKLDX
0.25
× tCK – 1050
0.25
× tCK – 750
—
ps
211
DQSn preamble start4
tDDKHMP
–0.25
× tCK
–0.25
× tCK
—ps
212
DQSn epilogue end5
tDDKHME
–600
600
ps
Notes:
1.
All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
2.
tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 410 ps before
the CK/CK crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval
from –410 to +677 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3.
Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4.
Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5.
All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation.
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| MSC7115VM800 | 功能描述:IC DSP PROCESSOR 16BIT 400MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC7116 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7116_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7116VF1000 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 7116 STARLITE PB-BEARING RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MSC7116VM1000 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 7116 STARLITE - PBF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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