參數(shù)資料
型號： MSC7116VM1000
廠商： Freescale Semiconductor
文件頁數(shù)： 15/60頁
文件大小： 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標準包裝： 90
系列： StarCore
類型： 定點
接口： 主機接口，I²C，UART
時鐘速率： 266MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 400kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freescale Semiconductor
22
2.5.2
Configuring Clock Frequencies
This section describes important requirements for configuring clock frequencies in the MSC7116 device when using the PLL
block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency FCLKIN. The output
of the divider block is the input to the multiplier block.
PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the
loop frequency FLOOP.
RNG field. Selects the available PLL frequency range for FVCO, either FLOOP when the RNG bit is set (1) or FLOOP/2
when the RNG bit is cleared (0).
CKSEL field. Selects FCLKIN, FVCO, or FVCO/2 as the source for the core clock.
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x
Reference Manual for details on the clock programming model.
2.5.2.1
PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10–25 MHz.
The output frequency of the PLL multiplier must be in the range 266–532 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2
Input Division Factors and Corresponding CLKIN Frequency Range
The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9.
Table 9. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Field Value
Input Divide
Factor
CLKIN Frequency Range
Comments
0x00
1
10 to 25 MHz
Input Division by 1
0x01
2
20 to 50 MHz
Input Division by 2
0x02
3
30 to 75 MHz
Input Division by 3
0x03
4
40 to 100 MHz
Input Division by 4
0x04
5
50 to 100 MHz
Input Division by 5
0x05
6
60 to 100 MHz
Input Division by 6
0x06
7
70 to 100 MHz
Input Division by 7
0x07
8
80 to 100 MHz
Input Division by 8
0x08
9
90 to 100 MHz
Input Division by 9
0x09
10
100 MHz
Input Division by 10
Note:
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10.
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