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| 型號： | MSC7116VM1000 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 26/60頁 |
| 文件大小： | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | 定點 |
| 接口： | 主機接口，I²C，UART |
| 時鐘速率： | 266MHz |
| 非易失內存： | ROM（8 kB） |
| 芯片上RAM： | 400kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA |
| 供應商設備封裝： | 400-MAPBGA（17x17） |
| 包裝： | 托盤 |
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MSC7116 Data Sheet, Rev. 13
Electrical Characteristics
Freescale Semiconductor
32
2.5.7
HDI16 Signals
Table 25. Host Interface (HDI16) Timing1, 2
No.
Characteristics3
Expression
Value
Unit
40
Host Interface Clock period
TCORE
Note 1
ns
44a
Read data strobe minimum assertion width4
HACK read minimum assertion width
2.0
× TCORE + 9.0
Note 11
ns
44b
Read data strobe minimum deassertion width4
HACK read minimum deassertion width
1.5
× TCORE
Note 11
ns
44c
Read data strobe minimum deassertion width4 after “Last Data Register”
reads5,6, or between two consecutive CVR, ICR, or ISR reads7
HACK minimum deassertion width after “Last Data Register” reads5,6
2.5
× TCORE
Note 11
ns
45
Write data strobe minimum assertion width8
HACK write minimum assertion width
1.5
× TCORE
Note 11
ns
46
Write data strobe minimum deassertion width8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes5
2.5
× TCORE
Note 11
ns
47
Host data input minimum setup time before write data strobe deassertion8
Host data input minimum setup time before HACK write deassertion
—
2.5
ns
48
Host data input minimum hold time after write data strobe deassertion8
Host data input minimum hold time after HACK write deassertion
—
2.5
ns
49
Read data strobe minimum assertion to output data active from high
impedance4
HACK read minimum assertion to output data active from high impedance
—
1.0
ns
50
Read data strobe maximum assertion to output data valid4
HACK read maximum assertion to output data valid
(2.0
× TCORE) + 8.0
Note 11
ns
51
Read data strobe maximum deassertion to output data high impedance4
HACK read maximum deassertion to output data high impedance
—
9.0
ns
52
Output data minimum hold time after read data strobe deassertion4
Output data minimum hold time after HACK read deassertion
—
1.0
ns
53
HCS[1–2] minimum assertion to read data strobe assertion4
—0.5
ns
54
HCS[1–2] minimum assertion to write data strobe assertion8
—0.0
ns
55
HCS[1–2] maximum assertion to output data valid
(2.0
× TCORE) + 6.0
Note 11
ns
56
HCS[1–2] minimum hold time after data strobe deassertion9
—0.5
ns
57
HA[0–2], HRW minimum setup time before data strobe assertion9
—5.0
ns
58
HA[0–2], HRW minimum hold time after data strobe deassertion9
—5.0
ns
61
Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read4, 5, 10
(3.0
× TCORE) + 6.0
Note 11
ns
62
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write5,8,10
(3.0
× TCORE) + 6.0
Note 11
ns
63
Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
(2.0
× TCORE) + 1.0
Note 11
ns
64
Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
(5.0
× TCORE) + 6.0
Note 11
ns
Notes:
1.
TCORE = core clock period. At 300 MHz, TCORE = 3.333 ns.
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3.
VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, CL = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings.
4.
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5.
For 64-bit transfers, the “l(fā)ast data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6.
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RX[0–3] registers without first
polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7.
This timing is applicable only if two consecutive reads from one of these registers are executed.
8.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
11. Compute the value using the expression.
12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe
modes is based on timings 57 and 58.
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