參數(shù)資料
型號: MSC7116VM1000
廠商: Freescale Semiconductor
文件頁數(shù): 39/60頁
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類型: 定點
接口: 主機(jī)接口,I²C,UART
時鐘速率: 266MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 400kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freescale Semiconductor
44
3.2.2.2
Case 2
The power-up sequence is as follows:
1.
Turn on the VDDIO (3.3 V) supply first.
2.
Turn on the VDDC (1.2 V) and VDDM (2.5 V) supplies simultaneously (second).
3.
Turn on the VREF (1.25 V) supply last (third).
Note:
Make sure that the time interval between the ramp-up of VDDIO and VDDC/VDDM is less than 10 ms.
The power-down sequence is as follows:
1.
Turn off the VREF (1.25 V) supply first.
2.
Turn off the VDDM (2.5 V) supply second.
3.
Turn off the VDDC (1.2 V) supply third.
4.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 31 for relative timing for Case 2.
Figure 31. Voltage Sequencing Case 2
Time
Vo
lt
a
g
e
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
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