參數(shù)資料
型號: MSC7119VF1200
廠商: Freescale Semiconductor
文件頁數(shù): 14/60頁
文件大小: 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標準包裝: 90
系列: StarCore
類型: 定點
接口: 主機接口,I²C,UART
時鐘速率: 300MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 464kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤
Electrical Characteristics
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
21
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50
Ω transmission line. For any additional pF, use the
following equations to compute the delay:
— Standard interface: 2.45 + (0.054
× C
load) ns
— DDR interface: 1.6 + (0.002
× C
load) ns
2.5.1
Clock and Timing Signals
The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see
Section 2.5.2 for the allowable ranges when using the PLL).
Table 6. Maximum Frequencies
Characteristic
Maximum in MHz
Core clock frequency (CLOCK)
300
External output clock frequency (CLKO)
75
Memory clock frequency (CK, CK)
150
TDM clock frequency (TxRCK, TxTCK)
50
Table 7. Clock Frequencies in MHz
Characteristic
Symbol
Min
Max
CLKIN frequency
FCLKIN
10
100
CLOCK frequency
FCORE
300
CK, CK frequency
FCK
150
TDMxRCK, TDMxTCK frequency
FTDMCK
—50
CLKO frequency
FCKO
—75
AHB/IPBus/APB clock frequency
FBCK
150
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 8. System Clock Parameters
Characteristic
Min
Max
Unit
CLKIN frequency
10
100
MHz
CLKIN slope
—5
ns
CLKIN frequency jitter (peak-to-peak)
1000
ps
CLKO frequency jitter (peak-to-peak)
150
ps
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