參數資料
型號： MSC7119VF1200
廠商： Freescale Semiconductor
文件頁數： 52/60頁
文件大?。?/td> 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標準包裝： 90
系列： StarCore
類型： 定點
接口： 主機接口，I²C，UART
時鐘速率： 300MHz
非易失內存： ROM（8 kB）
芯片上RAM： 464kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應商設備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
56
3.5.3
General Routing
The general routing considerations for the DDR are as follows:
All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
Minimize data bit jitter by trace matching.
3.5.4
Routing Clock Distribution
The DDR clock distribution considerations are as follows:
DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
For route traces as for any other differential signals:
— Maintain proper difference pair spacing.
— Match pair traces within 25 mm.
Match all clock traces to within 100 mm.
Keep all clocks equally loaded in the system.
Route clocks on inner critical layers.
3.5.5
Data Routing
The DDR data routing considerations are as follows:
Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
Take care to match trace lengths, which is extremely important.
To make trace matching easier, let adjacent groups be routed on alternate critical layers.
Pin swap bits within a byte group to facilitate routing (discrete case).
Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the design for readjustments as needed.
DDR data group separation:
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
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相關代理商/技術參數
參數描述
MSC7119VM1200 功能描述:數字信號處理器和控制器 - DSP, DSC FASTSTAR DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MSC711XADS 功能描述:開發(fā)板和工具包 - 其他處理器 DEV SYS FOR FSL 711X DEV RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MSC711XEVM 功能描述:開發(fā)板和工具包 - 其他處理器 EVAL KIT W/FULL LIC CW RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MSC711XEVMT 功能描述:KIT EVAL W/FULL LIC CW RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產零件編號 系列:* 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關產品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP
MSC7121VRF 制造商:Freescale Semiconductor 功能描述:GPON UMC 140 MHZ - Trays
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