After a power-on reset, the PLL is b" />
參數(shù)資料
型號(hào)： MSC7119VF1200
廠商： Freescale Semiconductor
文件頁數(shù)： 48/60頁
文件大?。?/td> 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： 定點(diǎn)
接口： 主機(jī)接口，I²C，UART
時(shí)鐘速率： 300MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 464kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
52
3.4.3
Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates
slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher
speed. The MSC7119 can boot from an external host through the HDI16 or download a user program through the I2C port. The
boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35.
See the MSC711x Reference Manual for details of boot program operation.
3.4.3.1
HDI16 Boot
If the MSC7119 device boots from an external host through the HDI16, the port is configured as follows:
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
Table 35. Boot Mode Source Selection
BM[3–0]
Boot
Port
Input Clock
Frequency
Clock
Divide
PLL
CKSEL
RNG
Bit
Core Clock
Frequency
Comments
HDI Boot Modes
0000
HDI16
< Fmax
N/A
00
0
< Fmax
Not clocked by the PLL.
Can boot as 8- or 16-bit HDI.
0101
HDI16
22.2-25 MHz
1
12
11
1
266–300 MHz
Can boot as 8- or 16-bit HDI.
0010
HDI16
25-33.3 MHz
2
32
01
1
200–266 MHz
0111
HDI16
33-66 MHz
3
12
11
1
132–264 MHz
0100
HDI16
44.3-50 MHz
2
12
11
1
266–300 MHz
SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins
1000
SPI (SW)
< Fmax
N/A
00
0
< Fmax
The boot program automatically
determines whether EEPROM
or Flash memory.
1001
SPI (SW)
15.6-25 MHz
1
17
11
0
133–212.5 MHz
1010
SPI (SW)
33-50 MHz
2
16
11
0
132–200 MHz
1011
SPI (SW)
44.3-75 MHz
3
18
11
0
133–225 MHz
SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins
1100
SPI (SW)
< Fmax
N/A
00
0
< Fmax
Boots through different set of
pins.
I2C Boot Modes
0001
I2C
< 100 MHz
N/A
00
0
< 100 MHz
Not clocked by the PLL.
I2C is limited to a maximum bit
rate of 400 Kbps. With a clock
divider of 128, this limits the
maximum input clock frequency
to 100 MHz.
Reserved
0011
Reserved
—
0110
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
Notes:
1.
The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.
2.
The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.
3.
Fmax is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.
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