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參數(shù)資料
| 型號： | MSC7170-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 5x7 Dot Character x 16-Digit x 2-Line Display Controller/Driver with Keyscan Function |
| 中文描述： | 5x7點字符× 16位× 2行顯示控制器/驅(qū)動器與鍵盤掃描功能 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MSC7170-01 |
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Semiconductor
MSC7170-01
14/27
FEDL7170-03
FUNCTIONAL DESCRIPTION
The MSC7170-01 (Dot Matrix VF Segment Driver) in conjunction with the MSC7171 (Dot Matrix
VF Grid Driver) is capable of controlling a variety of dot matrix VF displays and keyboards. The
MSC7170-01 is designed to drive the anodes of up to 32 dot matrix digits in two lines. Each digit
is a 5
￥
7 matrix of anodes, or dots, which requires a total of 70 segment driver outputs. There are
two extra segment outputs for supplying drive to dedicated annunciators. The grid drivers of the
MSC7171 are controlled by the MSC7170-01 through a two-line serial interface and a duty cycle
control line, DUTY (see APPLICATION CIRCUIT). Additionally, the MSC7170-01 provides 10-
bit digital dimming of all display data, a 5
￥
6 keyscan function allowing control of up to 30 key
pads and a low-power standby mode. The MSC7170-01 is controlled through a standard SPI
interface.
All MSC7170-01 internal timings are generated through an external 4 MHz (typ) ceramic
oscillator. One display cycle is defined as up to 16384 periods of the 4 MHz (250 ns) reference in
increments of 1024 periods, one for each pair of digits displayed. Display intensity is determined
by the duty cycle of the DUTY output within one display increment divided by the total number
of increments, or character pairs, displayed (see Display Duty Cycle Set and Number of Display
Digit Pairs Set commands below). The maximum duty cycle is defined as 976 out of 1024
increments or 95.3 percent.
The MSC7170-01 is capable of synchronizing the DUTY signal with an AC filament to avoid
visible flicker during dimming conditions. This is required in VF tubes of greater than 100 mm,
equivalent to 14 digits, in length. Synchronization is accomplished by alternately initiating
display cycles coincident with rising and falling edges of the filament voltage. Upon completion
of a rising/falling edge display cycle, the MSC7170-01 will wait for a falling/rising edge before
initiating the next display cycle. The MSC7170-01 detects rising and falling edges of a CMOS-
compatible SYNC input derived directly from the filament voltage. The amount of hold time
between display cycles varies between no delay as a minimum and the period of the filament
voltage as maximum. The amount of delay should be consistent for all display cycles assuming
that the filament frequency is well defined.
The MSC7170-01 is controlled through a Serial Peripheral Interface (SPI) compatible communi-
cations port. The SPI is a high-speed synchronous serial I/O port that shifts a serial bit stream of
eight data bits into or out of a device at a bit transfer rate programmed in a controlling device.
The figure below shows a typical connection of the SPI for communications between a master
(radio microprocessor) and slave (MSC7170-01). Three I/O pins are associated with the SPI
interface — SPI slave-in master-out (SIMO), SPI slave-out master-in (SOMI), and SPI serial clock
(SCLK). Additionally, a separate input pin is used to enable the MSC7170-01 to communicate
with the microprocessor through this interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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