參數(shù)資料
型號(hào)： MSC7170-01
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 5x7 Dot Character x 16-Digit x 2-Line Display Controller/Driver with Keyscan Function
中文描述： 5x7點(diǎn)字符× 16位× 2行顯示控制器/驅(qū)動(dòng)器與鍵盤(pán)掃描功能
文件頁(yè)數(shù)： 15/27頁(yè)
文件大?。?/td> 253K
代理商： MSC7170-01
Semiconductor
MSC7170-01
15/27
FEDL7170-03
Serial Input Buffer
MASTER
SIMO
SOMI
SCLK
Microprocessor
MSB
LSB
Shift Register
Serial Input Buffer
SLAVE
SIMO
SOMI
SCLK
MSC7170-01
MSB
LSB
Slave In/Master Out
Slave Out/Master In
Enable
Serial Clock
Shift Register
SPI Master/Slave Connection
The microprocessor provides the serial clock (500 kHz typ.) to all devices on the SPI network with
a CLOCK POLARITY of 1 (inactive level is high). Data is transferred from the master
(microprocessor) to the salve (MSC7170-01) over the SIMO line, while data is transferred from
the slave to the master over the SOMI line. Data is clocked out of the transmitting device on the
falling edge of SCLK and latched into the receiving device with the rising edge of SCLK. ALL data
transmissions are made MSB (b7) first.
A typical data transfer cycle between the microprocessor and the MSC7170-01 is initiated by first
bringing the
ENABLE
line low. The first byte transmitted defines the command or operation to
be executed. All remaining bytes received, prior to
ENABLE
being returned high, are treated as
data bytes for that operation. Each command or operation executed requires a separate
ENABLE
transfer cycle.
The maximum waiting period between byte transfers, measured from MSB to LSB, is 20 msec.
All activity on the SCLK and SIMO pins while
ENABLE
is high is ignored. Additionally, the
SOMI pin shall be in a tri-state condition when
ENABLE
is high so that other SPI devices on the
network may drive the line without contention.
The MSC7170-01 controls up to 30 key pads via a 5 controls up to 30 key pads via a 5
￥
6 key scan
circuit. COL1 to 6 (inputs) and ROW1 to 5 (outputs) are connected to an external switch matrix
with an impedance of 500
W
max. The ROW1 to 5 outputs start scanning only when a depression
or release of any key is detected. Upon completion of the first keyscan cycle, see Figure 6, the
keyboard interrupt,
KBINT
, output is pulled low to indicate availability of new keyscan data. The
keyscan circuit continues to scan and
KBINT
remains low until the keyscan data has been read
using the Keyscan Data Output Command. In the event of a multiple key depression, a second
interrupt will be generated following the clearing of the first interrupt. A stuck key switch will
not generate multiple interrupts since only state transitions are detected by the keyscan circuitry.
Keyscan data may be read without stopping the keyscan by using the Null Command. The
keyscan data is transmitted to the microprocessor by rows as shown in the Output Data Bytes
section. The output of keyscan data wraps around to the first byte for SPI transactions of more
than six bytes. After completion of the last keyscan cycle all ROW outputs go to low level.
相關(guān)PDF資料
PDF描述
MSC80196 RF & Microwave Transistors General Purpose Linear Applications(用于通用線性電路的RF和微波晶體管)
MSC80197 RF & Microwave Transistors General Purpose Linear Applications(用于通用線性電路的RF和微波晶體管)
MSC81002 RF & Microwave Transistors General Purpose Amplifier Applications(用于通用放大器的RF和微波晶體管)
MSC81005 RF & Microwave Transistors General Purpose Amplifier Applications(用于通用放大器的RF和微波晶體管)
MSC81010 RF & Microwave Transistors General Purpose Amplifier Applications(用于通用放大器的RF和微波晶體管)
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