參數(shù)資料
型號(hào)： MSC8101M1375F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, LEAD FREE, PLASTIC, BGA-332
文件頁(yè)數(shù)： 41/104頁(yè)
文件大?。?/td> 1811K
代理商： MSC8101M1375F
MSC8101 Technical Data, Rev. 18
Freescale Semiconductor
2-1
Physical and Electrical Specifications
2
This document contains detailed information on environmental limits, power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MSC8101 communications processor, mask set 2K87M. For
additional information, see the MSC8101 Reference Manual.
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another
specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation
of process parameter values in one direction. The minimum specification is calculated using the worst case for the
same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the
same device with a “minimum” value for another specification; adding a maximum to a minimum represents a
condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8101.
CAUTION
This device contains circuitry protecting against damage due to
high static voltage or electrical fields; however, normal precautions
should be taken to avoid exceeding maximum voltage ratings.
Reliability is enhanced if unused inputs are tied to an appropriate
logic voltage level (for example, either GND or VCC).
Table 2-1.
Absolute Maximum Ratings2
Rating
Symbol
Value
Unit
Core supply voltage3
VDD
–0.2 to 1.7
V
PLL supply voltage3
VCCSYN
–0.2 to 1.7
V
I/O supply voltage3
VDDH
–0.2 to 3.6
V
Input voltage3
VIN
(GND – 0.2) to 3.6
V
Maximum operating temperature range4
TJ
–40 to 120
°C
Storage temperature range
TSTG
–55 to +150
°C
Notes:
1.
Functional operating conditions are given in Table 2-2.
2.
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3.
The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In
turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not
exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at
any time, including during power-on reset. See Section 4.2,
information.
4.
Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature
(TJ).
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