參數(shù)資料
型號: MSC8144ETVT1000A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 57/80頁
文件大小: 1251K
代理商: MSC8144ETVT1000A
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
60
2.6.11
ATM/UTOPIA/POS Timing
Table 47 provides the ATM/UTOPIA/POS input and output AC timing specifications.
Figure 32 provides the AC test load for the ATM/UTOPIA/POS.
Figure 33 shows the ATM/UTOPIA/UTOPIA timing with external clock.
Table 47. ATM/UTOPIA/POS AC Timing (External Clock) Specifications
Characteristic
Symbol
Min
Max
Unit
Outputs—External clock delay
tUEKHOV
19
ns
Outputs—External clock High Impedance1
tUEKHOX
19
ns
Inputs—External clock input setup time
tUEIVKH
4ns
Inputs—External clock input hold time
tUEIXKH
1ns
Notes:
1.
Not tested. Guaranteed by design.
2.
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams
also apply when the falling edge is the active edge.
Figure 32. ATM/UTOPIA/POS AC Test Load
Figure 33. ATM/UTOPIAPOS AC Timing (External Clock)
Output
Z0 = 50 Ω
VDD/2
RL = 50 Ω
CLK (input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
Output Signals:
tUEKHOX
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