參數(shù)資料
型號： MSC8254SVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 18/68頁
文件大?。?/td> 909K
代理商： MSC8254SVT800B
Electrical Characteristics
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 4
Freescale Semiconductor
25
Table 4 describes thermal characteristics of the MSC8254 for the FC-PBGA packages.
2.4
CLKIN Requirements
Table 5 summarizes the required characteristics for the CLKIN signal.
Table 4. Thermal Characteristics for the MSC8254
Characteristic
Symbol
FC-PBGA
29
× 29 mm2
Unit
Natural
Convection
200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2
RθJA
18
12
°C/W
Junction-to-ambient, four-layer board1, 2
RθJA
13
9
°C/W
Junction-to-board (bottom)3
RθJB
5
°C/W
Junction-to-case4
RθJC
0.6
°C/W
Notes:
1.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESDC51-6. Thermal test board meets JEDEC
specification for the specified package.
3.
Junction-to-board thermal resistance determined per JEDEC JESD 51-8. Thermal test board meets JEDEC specification for
the specified package.
4.
Junction-to-case at the top of the package determined using MIL- STD-883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer
Table 5. CLKIN Requirements
Parameter/Condition1
Symbol
Min
Typ
Max
Unit
Notes
CLKIN duty cycle
—
40
—
60
%
2
CLKIN slew rate
—
1
—
4
V/ns
3
CLKIN peak period jitter
—
±150
ps
—
CLKIN jitter phase noise at –56 dBc
—
500
KHz
4
AC input swing limits
ΔVAC
1.5
—
V
—
Input capacitance
CIN
——
15
pf
—
Notes:
1.
For clock frequencies, see the Clock chapter in the MSC8254 Reference Manual.
2.
Measured at the rising edge and/or the falling edge at VDDIO/2.
3.
Slew rate as measured from ±20% to 80% of voltage swing at clock input.
4.
Phase noise is calculated as FFT of TIE jitter.
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