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參數(shù)資料
| 型號： | MSC8254SVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 50/68頁 |
| 文件大?。?/td> | 909K |
| 代理商： | MSC8254SVT800B |
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MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 4
Hardware Design Considerations
Freescale Semiconductor
54
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8254 device is designed into a system.
3.1
Power Supply Ramp-Up Sequence
The following subsections describe the required device initialization sequence.
3.1.1
Clock, Reset, and Supply Coordination
Starting the device requires coordination between several inputs including: clock, reset, and power supplies. Follow this
guidelines when starting up an MSC8254 device:
PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the VDDIO supply.
TRST deassertion does not have to be synchronized with PORESET deassertion. However, TRST must be deasserted
before normal operation begins to ensure correct functionality of the device.
CLKIN should toggle at least 32 cycles before PORESET deassertion to guarantee correct device operation. The 32
cycles should only be counted from the time after VDDIO reaches its nominal value (see timing 1 in Figure 33).
CLKIN should either be stable low during ramp-up of VDDIO supply (and start its swings after ramp-up) or should
swing within VDDIO range during VDDIO ramp-up, so its amplitude grows as VDDIO grows during ramp-up.
Figure 33 shows a sequence in which VDDIO ramps-up after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
Note:
For details on power-on reset flow and duration, see the Reset chapter in the MSC8254 Reference Manual.
Figure 33. Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO
Vo
lt
a
g
e
Time
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET deasserted
1
VDDIO applied
VDDIO = Nominal
VDD = Nominal
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| MSC8254TVT1000B | 0-BIT, OTHER DSP, PBGA783 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| MSC8254TVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSPStarcore 4-core RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC8254TVT800B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSPStarcore 4-core RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC8256 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Six-Core Digital Signal Processor |
| MSC8256_11 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Six-Core Digital Signal Processor |
| MSC8256ETAG1000B | 制造商:Freescale Semiconductor 功能描述:DSP,STARCORE, 6-CORE - Bulk |
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