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參數(shù)資料
| 型號(hào)： | MSM6242BGS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 177K |
| 代理商： | MSM6242BGS |
Semiconductor
MSM6242B
40
SUPPLEMENTARY DESCRIPTION
When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is
assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the
HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1
generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ
FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit
does not become "1".
Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t
1, t0, or
ITRPT/STND bit of register C
E, be sure to write "0" to the IRQ FLAG bit after writing to
make valid the IRQ FLAG = 1 to be generated after it.
*
The relationship between SDT.P OUT and IRQ FLAG bit is shown below:
STD.P OUT
IRQ FLAG bit
open
"L"
1
0
approx. 1.95 ms
TYPICAL APPLICATION — POWER SUPPLY CIRCUIT
Figure 20.
100
10K
VDD
MSM
6242B
VSS
4.7f
C
M
RL
1.5 x 2 = 3V
DRY CELLS
+5V
RL
VDD
MSM
6242B
VSS
4.7f
22f
100
51K
10K
+5V
Figure 19.
RIPPLE
OPERATING: 20mV P-P
BATTERY BACKUP: 0mV
VDD
MSM
6242B
VSS
100
4.7f
220
+5V
~ 6.5V
~
D1
RL
1.2 x 3 = 3.6V
Ni – Cd
1.2 x 3 = 3.6V
Ni – Cd
Figure 21.
4.7F: tantalum
VCE (SAT.) = 0.1V
B
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| MSM6242BGS-K | 制造商:ROHM Semiconductor 功能描述: |
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