參數(shù)資料
型號(hào): MSM6542-03RS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: 0.600 INCH, PLASTIC, DIP-24
文件頁(yè)數(shù): 18/54頁(yè)
文件大?。?/td> 406K
代理商: MSM6542-03RS
Semiconductor
MSM6542-01/02/03
92
e)
a-pm/am, a-h
20, and a-h10
In the 12-hour clock mode, the possible hours are from 1 A.M. to 12 A.M. and from 1 P.M.
to 12 P.M. When the bit is 1, it indicates P.M. When the bit is 0, it indicates A.M. In the 24-
hour clock mode, the possible hours are from 0 o'clock to 23 o'clock.
In the 12-hour clock mode, the a-h
20 bit is write-enabled. When 1 is written in it, an alarm
indicating an impossible time is generated. This is also true for the other registers: when
an impossible alarm time is set, no alarm is generated.
In the 24-hour clock mode, the a-pm/am bit is read- and write-enabled but its status is
assumed to be always the same as that of the r-pm/am bit.
f)
A-W
The A-W bits use the numbers from 0 to 6. Weight these bits in the same way as for R-W.
g)
The alarm registers are not incremented or decremented
A-ENABLE Register (Alarm ENABLE)
This register sets a comparison range for the real time counter and alarm registers.
The alarm registers outside the comparison range can be used as four-bit RAM areas. (The bits
marked an asterisk (*) in the register table can be used for write and read operations. When DP
is 1, however, write operation is not possible.)
The following table shows the relationships between the status of the A-ENABLE register bits
and alarm comparison ranges.
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