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參數(shù)資料
| 型號： | MSM6542-03RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 37/54頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MSM6542-03RS |
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Semiconductor
MSM6542-010/2/03
109
[Rewriting individual registers]
When bits other than the BANK 1/0 and DP bits are rewritten, the DP bit must be 0.
(a) R-S
1 to R-Y10 and R-W (For the MSM6542-3, 30s adjustment must not be performed
through pin 6 during rewriting.)
Read CF register
Idling
Idling for 126 s
RF = 1 ?
A carry is found
* 1
* 3
* 6
N
Y
* 5
* 2
* 1
* 2
REST
0
Alternatively,
STOP
1
Rewrite R-S1 to
R-Y10 and R-W
Rewrite R-S1 to
R-Y10 and R-W
CE register
REST
1
Alternatively,
CF register
STOP
1
OR
Idling for 65 s
Read CF register
* 4
*1
Dummy read to clear the READ
FLAG (RF) bit.
*2
Processing by other IC or wait
time to prevent unnecessary
readouts which occur frequently.
A measure is 50 ms.
*3, *4, *5
To assure that rewriting is com-
pleted before the next carry is
generated, the time required for
the step marked *5 must not be
longer than 1 s minus time re-
quired for steps marked *2 to *4.
*6
Time required for a carry pulse to
complete operation
*1
Wait time until a carry which may
be generated before 1 is written in
the REST (or STOP) bit is com-
pleted
*2
When 1 is written in the REST bit,
clocking is delayed for the dura-
tion during which the less-than-
second counter is cleared and
clocking is stopped until 0 is writ-
ten in the REST bit. When 1 is
written in the STOP bit, clocking
is delayed for the duration during
which clocking is stopped initial 0
is written in the STOP bit.
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