Contents-9
14.2.2 External XTCLK Input Control Function .................................................... 14-1
14.2.3 HOLD Input Control Function ................................................................... 14-1
14.2.4 WAIT Input Control Function .................................................................... 14-1
14.3 Peripheral Control Register (PRPHCON) ...................................................... 14-2
Chapter 15
External Interrupt Functions
15.1 Overview ........................................................................................................ 15-1
15.2 External Interrupt Registers ........................................................................... 15-1
15.2.1 Description of External Interrupt Registers ............................................... 15-2
(1) External interrupt control register 0 (EXI0CON) ....................................... 15-2
(2) External interrupt control register 1 (EXI1CON) ....................................... 15-3
(3) External interrupt control register 2 (EXI2CON) ....................................... 15-4
15.2.2 Example of External Interrupt-related Register Settings ........................... 15-5
15.3 EXINT0 to EXINT5 Interrupts ......................................................................... 15-6
Chapter 16
Interrupt Processing Functions
16.1 Overview ........................................................................................................ 16-1
16.2 Interrupt Function Registers ........................................................................... 16-2
16.3 Description of Interrupt Processing ................................................................ 16-3
16.3.1 Non-Maskable Interrupt (NMI) .................................................................. 16-3
16.3.2 Maskable Interrupts .................................................................................. 16-5
(1) Interrupt request registers (IRQ0 to IRQ4) ............................................... 16-5
(2) Interrupt enable registers (IE0 to IE4) ....................................................... 16-5
(3) Master interrupt enable flag (MIE) ............................................................ 16-5
(4) Master interrupt priority flag (MIPF) .......................................................... 16-5
(5) Interrupt priority control registers (IP0 to IP9) ........................................... 16-6
16.3.3 Priority Control of Maskable Interrupts ................................................... 16-10
16.4 IRQ, IE and IP Register Configurations for Each Interrupt .......................... 16-12
16.4.1 Interrupt Request Registers (IRQ0 to IRQ4) ........................................... 16-12
(1) Interrupt request register 0 (IRQ0) .......................................................... 16-12
(2) Interrupt request register 1 (IRQ1) .......................................................... 16-13
(3) Interrupt request register 2 (IRQ2) .......................................................... 16-14
(4) Interrupt request register 3 (IRQ3) .......................................................... 16-15
(5) Interrupt request register 4 (IRQ4) .......................................................... 16-16
16.4.2 Interrupt Enable Registers (IE0 to IE4) ................................................... 16-17
(1) Interrupt enable register 0 (IE0) .............................................................. 16-17
(2) Interrupt enable register 1 (IE1) .............................................................. 16-18
(3) Interrupt enable register 2 (IE2) .............................................................. 16-19
(4) Interrupt enable register 3 (IE3) .............................................................. 16-20
(5) Interrupt enable register 4 (IE4) .............................................................. 16-21