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參數(shù)資料
| 型號： | MSM7557 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Single Chip MSK Modem with Compandor for Cordless Telephone |
| 中文描述： | 單芯片MSK調制解調器無繩電話與Compandor |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 153K |
| 代理商： | MSM7557 |
8/25
MSM7557
Semiconductor
(Continued)
Name
BIT
FPS
Detect pattern
Receiver
Handset side
Base station
Handset side
Base station
V
DD
Power supply.
This device is sensitive to power supply noises as switched capacitor tequniques are utilized.
A bypass capacitor of more than 10
m
F between V
DD
and GND pin should be connected to ensure
the performance.
(Note : This pattern is for Japanese Cordless Telephone.)
RVE
RT
RD
FD
FPS
BIT
FDE
Frame synchronous signal detector control.
When digital "0" is applied to this pin, FD pin is fixed to "0" level. RT and RD always work.
When digital "1" is applied to this pin, frame synchronous detector works, and RT and RD pins are fixed
to "1" level untill synchronous signal detector detects frame synchronous signal and FD becomes "1" level.
Refer to Fig.3 (receive signal timing).
Bit synchronous signal detector control.
When BIT and FDE pins are digital "1" level and when bit synchronous signal and frame synchronous
signal are detected continously, FD becomes digital "1".
When BIT pin is digital "0" level and FDE pin is digital "1" level and when 16-bit frame synchronous
signal is detected, FD pin becomes digital "1" level.
Refer to FPS pin detection.
Frame synchronous pattern control.
Frame synchronous detector output.
When receive data correspond to detection pattern, FD pin is held to digital "1" level.
When FDE is applied to digital "0" level, FD pin is reset to digital "0" level.
And at the full power down state (PDN = "1", RVE = "0" ), FD pin is reset to digital "0" level.
Demodulator serial data output.
The data are synchronized with the re-generated timing clock of RT.
When FDE is digital "1" level and also FD is digital "0" level, RD is fixed to digital "1" level.
Receive data timing clock output.
This signal is re-generated by internal digital PLL. The falling edge of this clock output is coincident
with the transitions of RD.
The rising edge of RT can be used to latch the valid receive data.
When FDE pin is applied to digital "1" level and also FD pin output digital "0" level, RT pin is fixed to
digital "1" level. Refer to Fig.3.
Receive voice signal control.
Refer to RVO pin description.
(=9336H)
(=C4D6H)
(=A9336H)
(=AC4D6H)
1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0
1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0
1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0
0
0
1
1
0
1
0
1
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