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參數(shù)資料
| 型號： | MSM7662 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | NTSC/PAL Digital Video Decoder(NTSC/PAL制式數(shù)字視頻譯碼器) |
| 中文描述： | NTSC / PAL數(shù)字視頻解碼器（的NTSC / PAL制式數(shù)字視頻譯碼器） |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 369K |
| 代理商： | MSM7662 |
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Semiconductor
MSM7662
21/47
A/D Converter Support Signal
The waveform of the HSY signal, shown below, provides clamp timing to the A/D converter
when HSY clamp (digital clamp) is selected. The start and end edges of the clamp pulse have a
variable range from the sync chip to the pedestal position.
COLOR
BURST
CVBS
BURST
HSY
A/D Converter Support Signal
Output Timing
ITU-R.656 output
4T
Digital line {1716T (NTSC, 525), 1728T (PAL, 625)}
Digital active line
Digital line blanking
276T (NTSC, 525)
288T (PAL, 625)
Multiplexed video data
Cb0 Y00 Cr0 Cb1 Y10 Cr1 Y11
Video data block (1440T)
E
4T
S
E
T
SAV
EAV
: clock periods 37 ns normal (1/27 MHz)
: start of active video timing reference code
: end of active video timing reference code
ITU-R BT.656 Output (Data in one line in which video data presents)
During the blanking interval, data is output with the Y value.
Note:
Digital line 1716T (NTSC, 525) and 1728T (PAL, 625) are not maintained at the next line.
Digital active line 1440T of the line immediately after VVALID falls and the 10th or 11th
line after VSYNC_L rises will fluctuate due to pixel compensation. Especially when a
non-standard signal is input, the line immediately after VVALID falls will fluctuate
largely due to instability of the input signal. Due to phenomena such as an increase in
the number of lines for a standard signal and a decrease in the number of lines for a non-
standard signal, it may not be possible to guarantee correct EAV and SAV functionality.
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