
Semiconductor
MSM7662
32/47
Note:
Adaptive comb filter
2/3-line comb filter for NTSC
Comb filter/trap filter for PAL
3-line comb filter for NTSC
2-line cosine comb filter for PAL
Non-adaptive comb filter
Mode Register C (MRC)
Write only
<address: $02>
MRC[7]
NTSC/PAL Auto select
0: Fix
*1: Auto
*0: Use pixel position compensating circuit.
1: Do not use pixel position compensating circuit.
*0: (4:2:2)
1: (4:1:1)
*0: Use DECIMATOR at 2x sampling
1: Do not use DECIMATOR
MRC[6]
Sub Pixel Alignment
MRC[5]
Pixel Sampling Rate
MRC[4]
Data-pass control
Note:
MRC[3]
This register is valid when a 2x clock (27 MHz) is input.
SAV, EAV V-status
*0: During blanking, V = 1
1: During blanking, while VBI data is not
detected, V = 1
*0: 0 to 255
1: 16 to 235
Set to 0
MRC[2]
RGB output level
MRC[1:0]
Undefined
Horizontal Sync Trimmer (HSYT)
Write only
<address: $03>
HSYT[7:4]
HSYT[3:0]
HSY start trimmer (
¥
8 pixels)
HSY stop trimmer (
¥
8 pixels)
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
Sync. Threshold level adjust (STHR)
Write only
<address: $04>
STHR[7:0]
Sync. depth
$00 to $FF (*$1E): 0 to 255
Horizontal Sync Delay (HSDL)
Write only
<address: $05>
HSDL[7:0]
HSYNC_L delay trimmer (
¥
1 pixel)
$80 to $7F (*$00): –128 to +127 (–128 to +127
pixels)
Note:
In the internal sync separation (PLLSEL: Low) mode, the HSYNC_L sync signal output
position is adjusted.
In the external sync separation (PLLSEL: High) mode, the phase shift of the H-Sync
input and video signal input is adjusted.
Horizontal Valid Trimmer (HVALT) Write only
<address: $06>
HVALT[7:4] HVALID start trimmer (
¥
2 pixels) $8 to $7 (*$0): –8 to +7 (–16 to +14 pixels)
HVALT[3:0] HVALID stop trimmer (
¥
2 pixels) $8 to $7 (*$0): –8 to +7 (–16 to +14 pixels)