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參數(shù)資料
| 型號： | MSM80C51F-XXXRS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 21/39頁 |
| 文件大?。?/td> | 355K |
| 代理商： | MSM80C51F-XXXRS |
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Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN
= 100 pF ; Load Capacitance for all other outputs = 80 pF)
Parameter
Symbol
Min.
Max.
Unit
XTAL1, XTAL2 Oscillation Cycle
tCLCL
——
ns
ALE Signal Width
tLHLL
126
—
ns
Adderss Setup Time
(to ALE Falling Edge)
tAVLL
43
—
ns
Max.
—
Min.
83.3
2tCLCL – 40
1tCLCL – 40
Adderss Hold Time
(from ALE Falling Edge)
tLLAX
48
—
ns
—1tCLCL – 35
Instruction Data Read Time
(from ALE Falling Edge)
tLLIV
—4tCLCL – 100
ns
233
—
From ALE Falling Edge to
PSEN Falling Edge
tLLPL
58
—
ns
—1tCLCL – 25
PSEN Signal Width
tPLPH
215
—
ns
—3tCLCL – 35
Instruction Data Read Time
(from
PSEN Falling Edge)
tPLIV
—3tCLCL – 105
ns
145
—
Instruction Data Hold Time
(from
PSEN Rising Edge)
tPXIX
0—
ns
—0
Bus Floating Time after Instruction
Data Read (from
PSEN Rising Edge)
tPXIZ
—1tCLCL – 20
ns
63
—
Address Output Time from
PSEN Rising Edge
tPXAV
75
—
ns
—1tCLCL – 8
Instruction Data Read Time
(from Address Output)
tAVIV
—5tCLCL – 105
ns
312
—
Bus Floating Time (Address
Float from
PSEN Falling Edge)
tPLAZ
—0
ns
0—
12 MHz Clock
Variable Clock
See Guaranteed
Operating Range
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