參數資料
型號: MSM80C51F-XXXRS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁數: 25/39頁
文件大?。?/td> 355K
代理商: MSM80C51F-XXXRS
31/38
Semiconductor
MSM80C31F/80C51F
External Data Memory Access AC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =
100 pF ; load capacitance for all other outputs = 80 pF)
Parameter
Symbol
Min.
Max.
Unit
XTAL1, XTAL2 Oscillation Cycle
tCLCL
——
ns
ALE Single Width
tLHLL
126
ns
Adderss Setup Time
(to ALE Falling Edge)
tAVLL
43
ns
Max.
Min.
62.5
2tCLCL – 40
1tCLCL – 40
Adderss Hold Time
(from ALE Falling Edge)
tLLAX
48
ns
—1tCLCL – 35
12 MHz Clock
Variable Clock
RD Single Width
tRLRH
400
ns
—6tCLCL – 100
WR Single Width
tWLWH
400
ns
—6tCLCL – 100
RAM Data Read Time
(from
RD Single Falling Edge)
tRLDV
—5tCLCL – 165
ns
251
RAM Data Read Hold Time
(from
RD Single Rising Edge)
tRHDX
0—
ns
—0
Data Bus Floating Time
(from
RD Single Rising Edge)
tRHDZ
—2tCLCL – 70
ns
96
RAM Data Read Time
(from
ALE Single Falling Edge)
tLLDV
—8tCLCL – 150
ns
516
RAM Data Read Time
(from Address Output)
tAVDV
—9tCLCL – 165
ns
585
RD/WR Output Time from
ALE Falling Edge
tLLWL
150
3tCLCL + 50
ns
300
3tCLCL – 100
RD/WR Output Time from
Address Output
tAVWL
203
ns
—4tCLCL – 130
RD Output Time from Data Output
tQVWX
23
ns
—1tCLCL – 60
Time from Data Output to
WR Rising Edge
tQVWH
433
ns
—7tCLCL – 150
Data Hold Time (
WR Rising Edge)
tWHQX
33
ns
—1tCLCL – 50
Time from
RD Output to
Address Float
tRLAZ
—0
ns
0—
Time from
RD/WR Rising
Edge to ALE Rising Edge
tWHLH
43
1tCLCL + 100
ns
183
1tCLCL – 40
See Guaranteed
Operating Range
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