參數(shù)資料
型號(hào): MSM80C88A-10JS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44
封裝: 0.650 X 0.650 INCH, 1.27 MM PITCH, PLASTIC, QFJ-44
文件頁(yè)數(shù): 3/37頁(yè)
文件大?。?/td> 267K
代理商: MSM80C88A-10JS
11/37
Semiconductor
MSM80C88A-10RS/GS/JS
Minimum Mode (continued)
Notes: 1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are
to be inserted.
3. Two INTA cycles run back-to-back. The MSM80C88A-10 LOCAL ADDR/DATA
BUS is floating during both INTA cycles. Control signals shown for second INTA
cycle.
4. Signals at MSM82C84A-2 shown for reference only.
5. All timing measurements are made at 1.5 V unless otherwise noted.
VIH
VIL
IO/M, SS0
A19/S6 - A16/S3
ALE
AD7 - AD0
DEN
WR
AD7 - AD0
DT/R
INTA
DEN
Write Cycle
(NOTE 1)
RD, INTA
DT/R = VOH
INTA Cycle
(NOTES 1 & 3)
(RD, WR = VOH
BHE = VOL)
CLK (MSM82C84A-2 Output)
tCLCL
tCHCTV
tCHCL
tCH1CH2
tCL2CL1
T2
T3
T4
TW
tCLCH
tCLAV
tCLLH
tCLAX
tCLDV
tCHDX
A19 - A16
S6 - S3
tLHLL
tLLAX
tAVAL
tCLDV
tCLAV
tCVCTV
tLLAX
tAVAL
tCVCTV
tWLWH
tCLAZ
tCHCTV
tCVCTV
tCVCTX
tCLAV
tCHCTV
tCLDX
tCVCTX
tDVCL
tCVCTX
tCHDX
AD7 - AD0
Data Out
Float
Pointer
Float
Invalid Address
Software Halt
RD, WR, INTA = VOH
DT/R = Indeterminate
tCLAX
tWHDX
Software Halt TCLAV
tCHLL
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參數(shù)描述
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