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參數(shù)資料
| 型號： | MSM82C37B-5GS-2K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大小： | 330K |
| 代理商： | MSM82C37B-5GS-2K |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Memory-memory Transfer
Memory-memory transfers are used to transfer data blocks from one memory area to another.
Memory-memory transfers require a total of eight states to complete a single transfer four states
(S11 thru S14) for reading from memory, and four states (S21 thru S24) for writing into memory.
These states are similar to I/O-memory transfer states, and are distinguished by using two-digit
numbers. In memory-memory transfers, channel 0 is used for reading data from the source area,
and channel 1 is used for writing data into the destination area. During the initial four states,
data specified by the channel 0 address is read from the memory when MEMR is made active,
and is taken in the MSM82C37B-5 temporary register. Then during the latter four states, the data
in the temporary register is written in the address specified by channel 1. This completes the
transfer of one byte of data. With channel 0 and channel 1 addresses subsequently incremented
(or decremented) by 1, and channel 0, 1 word count decremented by 1, this operation is repeated.
The transfer is terminated when the word count reaches FFFF(H) from 0000(H), or when an EOP
input is applied from an external source. Note that there is no DACK output signal during this
transfer.
The following preparations in programming are requiring to enable memory-memory transfers
to be started.
Command Register Setting
Memory-memory transfers are enabled by setting bit 0. Channel 0 address can be held for all
transfers by setting bit 1. This setting can be used to enable 1-word contents of the source area
to be written into the entire destination area.
Mode Register Setting
The transfer type destination is disregarded in channels 0 and 1. Memory-memory transfers are
always executed in block transfer mode.
Request Register Setting
Memory-memory transfers are started by setting the channel 0 request bit.
Mask Register Setting
Mask bits for all channels are set to prevent selection of any other channel apart from channel
0.
Word Count Register Setting
The channel 1 word count is validated, while the channel 0 word count is disregarded.
In order to autoinitialize both channels, it is necessary to write the same values into both word
count registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C43GS-K | 20 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| MSM82C51A-2GS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
| MSM82C54-2RS | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| MSM82C54-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C37B-5JS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44 |
| MSM82C37B-5RS | 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40 |
| MSM82C37B-5VJS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
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