參數(shù)資料
型號(hào)： MSM82C37B-5GS-2K
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： DMA控制器
英文描述： 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù)： 9/35頁(yè)
文件大?。?/td> 330K
代理商： MSM82C37B-5GS-2K
16/33
Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF TRANSFER TYPES
MSM82C37B-5 transfers between an I/O and memory devices, or transfers between memory
devices. The three types of transfers between I/O and memory devices are read, write, and
verify.
I/O-Memory Transfers
The operational states during an I/O-memory transfer are S1, S2, S3, and S4.
In the S1 state, an AEN output is changed to high level to indicate that the control signal from
the MSM82C37B-5 is valid. The eight lower order bits of the transfer address are obtained from
A0 thru A7, and the eight higher order bits are obtained from DB0 thru DB7. The ADSTB output
is changed to high level at this time to set the eight higher order bits in an external address latch,
and the DACK output is made active for the channel where the DMA request is acknowledged.
Where there is no change in the eight higher bit transfer address during demand and block mode
transfers, however, the S1 state is omitted.
In the S2 state, the IOR or MEMR output is changed to low level.
In the S3 state, IOW or MEMW is changed to low level. Where compressed timing is used,
however, the S3 state is omitted.
The S2 and S3 states are I/O or memory input/output timing control states. In the S4 state, IOR,
IOW, MEMR, and MEMW are changed to high level, and the word count register is decremented
by 1 while the address register is incremented (or decremented) by 1. This completes the DMA
transfer of one word.
Note that in I/O-memory transfers, data is transferred directly without being taken in by the
MSM82C37B-5. The differences in the three types of I/O-memory transfers are indicated below.
Read Transfer
Data is transferd from memory to the I/O device by changing MEMR and lOW to low level.
MEMW and IOR are kept at high level during this time.
Write Transfer
Data is transferred from the I/O device to memory by changing MEMW and IOR to low level.
MEMR and IOW are kept at high level during this time.
Note that writing and reading in these write and read transfers are with respect to the memory.
Verify Transfer
Although verify transfers involve the same operations as write and read transfers (such as
transfer address generation and EOP input responses),they are in fact pseudo transfers where
all I/O and memory reading/writing control signals are kept inactive. READY inputs are
disregarded in verify transfers.
相關(guān)PDF資料
PDF描述
MSM82C43GS-K 20 I/O, PIA-GENERAL PURPOSE, PDSO24
MSM82C51A-2GS 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32
MSM82C54-2GS-K 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
MSM82C54-2RS 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24
MSM82C54-2GS-K 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM82C37B-5JS 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHZ, DMA CONTROLLER, PQCC44
MSM82C37B-5RS 制造商:OK International 功能描述:4 CHANNEL(S), 5 MHz, DMA CONTROLLER, PDIP40
MSM82C37B-5VJS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER
MSM82C43 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER
MSM82C51A-2GS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
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