參數(shù)資料
型號(hào): MSM82C37B-5RS
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: Programmable DMA Controller(可編程DMA控制器)
中文描述: 可編程DMA控制器(可編程DMA的控制器)
文件頁(yè)數(shù): 23/33頁(yè)
文件大?。?/td> 209K
代理商: MSM82C37B-5RS
23/33
Semiconductor
MSM82C37B-5RS/GS/VJS
Mode Register
Each channel is equipped with a 6-bit write-only mode register, which is decided by setting DB
0
,
DB
1
which channel is to be written when writing from CPU is programming status. The bit
description is outlined in Figure 4.
This register is not cleared by Reset or Master Clear instruction.
DB
7
00: Channel 0 Selected
01: Channle 1 Selected
10: Channel 2 Selected
11: Channle 3 Selected
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
00: Verify Transfer
01: Write Transfer
10: Read Transfer
11: Disabled
(Invalid When DB
6
·DB
7
="11")
0: Auto Initialize Disabled
1: Auto Initialize Enabled
0: Address Increment (+1) Selected
1: Address Decrement (-1) Selected
00: Demand Transfer Mode Selected
01: Single Transfer Mode Selected
10: Block Transfer Mode Selected
11: Cascade Mode Selected
Fig.4 Mode Register
Request Register
In addition to using the DREQ signal, the MSM82C37B-5 can request DMA transfers by software
means. This involves setting the request bit of request register. Each channel has a corresponding
request bit in the request register, and the order of priority of these bits is determined by the
priority decision circuit irrespective of the mask register. DMA transfers are acknowledged in
accordance with the decided order of priority.
All request bits are reset when the TC is reached, and when the request bit of a certain channel
has been received, all other request bits are cleared. When a memory-memory transfer is
commenced, the channel 0 request bit is set. The bit description is outlined in Figure 5.
DB
7
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
0: Request Bit Cleared
1: Request Bit Set
Not Used
Fig.5 Request Register
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