參數(shù)資料
型號: MSM82C37B-5RS
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: Programmable DMA Controller(可編程DMA控制器)
中文描述: 可編程DMA控制器(可編程DMA的控制器)
文件頁數(shù): 25/33頁
文件大?。?/td> 209K
代理商: MSM82C37B-5RS
25/33
Semiconductor
MSM82C37B-5RS/GS/VJS
Status Register
This register is a read-only register used in CPU reading of the MSM82C37B-5 status. The four
higher order bits indicate the DMA transfer request status for each channel, ‘1’ being set when
the DREQ input signal is active.
The four lower order bits indicate whether the corresponding channel has reached the TC or not,
‘1’ being set when the TC status is reached. These four lower order bits are reset by status
register reading, or RESET input and master clearing. A description of each bit is outlined in
Figure 7
DB
7
0: Channel 0 Has Not Reached TC
1: Channel 0 Has Reached TC
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
0: Channel 1 Has Not Reached TC
1: Channel 1 Has Reached TC
0: Channel 2 Has Not Reached TC
1: Channel 2 Has Reached TC
0: Channel 3 Has Not Reached TC
1: Channel 3 Has Reached TC
0: Channel 0 Is Not Requesting
1: Channel 0 Is Requesting
0: Channel 1 Is Not Requesting
1: Channel 1 Is Requesting
0: Channel 2 Is Not Requesting
1: Channel 2 Is Requesting
0: Channel 3 Is Not Requesting
1: Channel 3 Is Requesting
Fig. 7 Status Register
Temporary Register
The temporary register is a register where transfer data is held temporarily during memory-
memory transfers. Since the last item of data to be transferred is held after completion of the
transfer, this item can be read by the CPU.
Software Command
The MSM82C37B-5 is equipped with software commands for executing special operations to
ensure proper programming. Software command is irrespective of data bus contents.
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參數(shù)描述
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