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參數(shù)資料
| 型號(hào)： | MSM82C55A-2RS |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 207K |
| 代理商： | MSM82C55A-2RS |
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Semiconductor
MSM82C55A-2RS/GS/VJS
1
D7
1
2
1
Type
3
4
6
5
7
8
1
0
D6
0
D5
0
D4
0
1
0
D3
0
1
0
1
0
D2
0
D1
1
0
1
0
1
0
1
0
D0
0
1
0
1
0
1
0
1
Output
Port A
Output
Input
Output
High Order 4 Bits
of Port C
Output
Input
Output
Input
Output
Port B
Input
Output
Input
Output
Input
Output
Input
Output
Control Word
Group A
Group B
Low Order 4 Bits
of Port C
Output
Input
Output
Ouput
Input
Output
Input
Output
Input
10
9
11
12
14
13
15
16
Notes: When used in mode 0 for both groups A and B
2. Mode 1 (Strobe input/output operation)
In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB (Strobe input)
When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)
This is the response signal for the STB. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of STB
and to low level at the rising edge of RD.
INTR (Interrupt request output)
This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge
of the RD when the INTE is set.
INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the
bit for PC2 is set.
Following is a description of the output operation of mode 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM82C55A-2VJS | 24 I/O, PIA-GENERAL PURPOSE, PQCC44 |
| MSM82C59A-2GS-K | 80C85AH; 80C86A; 80C88A COMPATIBLE, INTERRUPT CONTROLLER, PDSO32 |
| MSM82C84A-2GS-K | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
| MSM82C84A-2JS | OTHER CLOCK GENERATOR, PQCC20 |
| MSM83C154-XXJS | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM82C55A-2VJ3 | 制造商:OKI Semiconductor 功能描述:CPU I/OS EOL211209 制造商:ROHM Semiconductor 功能描述: |
| MSM82C55A-2VJS | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述:PERIPHERAL INTERFACE, 44 Pin, Plastic, PLCC 制造商:OKI Semiconductor 功能描述:PERIPHERAL INTERFACE, 44 Pin, Plastic, PLCC |
| MSM82C55A-2VJSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C59A-2GS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:PROGRAMMABLE INTERRUPT CONTROLLER |
| MSM82C59A-2GS-K | 制造商:ROHM Semiconductor 功能描述: |
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